{"version":"1.0","provider_name":"Escuela Superior de Inform\u00e1tica de UCLM","provider_url":"https:\/\/esi.uclm.es","title":"Charla: Dise\u00f1o de circuitos digitales sobre FPGA - Escuela Superior de Inform\u00e1tica de UCLM","type":"rich","width":600,"height":338,"html":"<blockquote class=\"wp-embedded-content\" data-secret=\"QFS1ob3qrB\"><a href=\"https:\/\/esi.uclm.es\/index.php\/events\/charla-diseno-de-circuitos-digitales-sobre-fpga\/\">Charla: Dise\u00f1o de circuitos digitales sobre FPGA<\/a><\/blockquote><iframe sandbox=\"allow-scripts\" security=\"restricted\" src=\"https:\/\/esi.uclm.es\/index.php\/events\/charla-diseno-de-circuitos-digitales-sobre-fpga\/embed\/#?secret=QFS1ob3qrB\" width=\"600\" height=\"338\" title=\"\u00abCharla: Dise\u00f1o de circuitos digitales sobre FPGA\u00bb \u2014 Escuela Superior de Inform\u00e1tica de UCLM\" data-secret=\"QFS1ob3qrB\" frameborder=\"0\" marginwidth=\"0\" marginheight=\"0\" scrolling=\"no\" class=\"wp-embedded-content\"><\/iframe><script>\n\/*! This file is auto-generated *\/\n!function(d,l){\"use strict\";l.querySelector&&d.addEventListener&&\"undefined\"!=typeof URL&&(d.wp=d.wp||{},d.wp.receiveEmbedMessage||(d.wp.receiveEmbedMessage=function(e){var t=e.data;if((t||t.secret||t.message||t.value)&&!\/[^a-zA-Z0-9]\/.test(t.secret)){for(var s,r,n,a=l.querySelectorAll('iframe[data-secret=\"'+t.secret+'\"]'),o=l.querySelectorAll('blockquote[data-secret=\"'+t.secret+'\"]'),c=new RegExp(\"^https?:$\",\"i\"),i=0;i<o.length;i++)o[i].style.display=\"none\";for(i=0;i<a.length;i++)s=a[i],e.source===s.contentWindow&&(s.removeAttribute(\"style\"),\"height\"===t.message?(1e3<(r=parseInt(t.value,10))?r=1e3:~~r<200&&(r=200),s.height=r):\"link\"===t.message&&(r=new URL(s.getAttribute(\"src\")),n=new URL(t.value),c.test(n.protocol))&&n.host===r.host&&l.activeElement===s&&(d.top.location.href=t.value))}},d.addEventListener(\"message\",d.wp.receiveEmbedMessage,!1),l.addEventListener(\"DOMContentLoaded\",function(){for(var e,t,s=l.querySelectorAll(\"iframe.wp-embedded-content\"),r=0;r<s.length;r++)(t=(e=s[r]).getAttribute(\"data-secret\"))||(t=Math.random().toString(36).substring(2,12),e.src+=\"#?secret=\"+t,e.setAttribute(\"data-secret\",t)),e.contentWindow.postMessage({message:\"ready\",secret:t},\"*\")},!1)))}(window,document);\n\/\/# sourceURL=https:\/\/esi.uclm.es\/wp-includes\/js\/wp-embed.min.js\n<\/script>\n","thumbnail_url":"http:\/\/esi.uclm.es\/assets\/uploads\/2024\/04\/FPGA.webp","thumbnail_width":1200,"thumbnail_height":720,"description":"Mi\u00e9rcoles 10 abril, 10:00 a.m. Ponentes: Ingeniera\u00a0D\u00f1a. Victorina Fern\u00e1ndez Gonz\u00e1lez\u00a0Responsable de Ingenier\u00eda de L\u00f3gica Programable de Cipherbit (Grupo Oes\u00eda) Ingeniero\u00a0D. David de la Fuente de San Venancio\u00a0Responsable de software del departamento Apoyo en Servicio en Tecnobit (Grupo Oes\u00eda) +info"}